A Statistical Circuit Optimization Algorithm under Thermal and Timing Constraints

Process Variation has become a crucial challenge on both interconnect delay and reliability of nanometer integrated circuit designs. Furthermore, the dramatic increase of power consumption and integration density has led to high operating temperature. Temperature, as well as electromigration (EM) and power, also significantly affects the delay and reliability of interconnects. Considering process variation, we use statistical methods to simultaneously optimize the circuit area, delay, power, thermal, and EM reliability by sizing circuit components (both wires and gates). We model the problem as a second-order conic program and solve it with the interior-point optimization method. Experimental results show that our statistical algorithm can efficiently find desired solutions that satisfy all delay, power, and thermal constraints.